Recent attempts to increase the performance of bipolar logic (i.e. electronic logic circuits incorporating bipolar transistors/devices) have resulted in fabrication processes which yield smaller, more densely packed bipolar devices. The use of these fabrication processes, including, for example, the so called self-aligned fabrication processes, permits the formation of bipolar transistors having structures formed to sub-micron resolution. Transistors formed using these processes tend to exhibit substantially decreased size and density, and substantially increased switching speeds, in comparison to prior art devices.
The following patents are of interest as showing various examples of self-aligning transistor fabrication processes and resulting devices.
U.S. Pat. No. 4,495,512 to Isaac et al., assigned to the assignee of the present invention, shows a bipolar transistor having a silicide extrinsic base contact with an overlying doped polysilicon layer. The silicide and polysilicon have coextensive apertures defining the intrinsic base and emitter regions. The extrinsic base region is formed by diffusing impurities from the doped polysilicon layer through the silicide layer.
U.S. Pat. No. 4,483,726 to Isaac et al., assigned to the assignee of the present invention, shows a bipolar transistor having a small, self-aligned sidewall contact to the extrinsic base. The extrinsic base region is fabricated by forming the doped contact/sidewall between two layers of insulating material, and diffusing impurities from the contact to form the extrinsic base region. The intrinsic base and emitter regions are formed in the silicon through an aperture defined by insulative sidewalls formed over the extrinsic base contact.
U.S. Pat. No. 4,319,932 to Jamboktar, assigned to the assignee of the present invention, shows a bipolar transistor formed by employing polysilicon base contacts self-aligned with respect to a diffusion or ion implantation window used to form emitter, intrinsic base, and raised subcollector regions. The polysilicon acts as a self-aligned impurity source to form the extrinsic base region therebelow, and after being coated with silicon dioxide on the surface and along the sidewalls of the diffusion or ion implantation window, as a mask.
U.S. Pat. No. 4,157,269 to Ning et al., assigned to the assignee of the present invention, shows a method of manufacturing a bipolar transistor having base contacts formed of polysilicon material and an emitter contact formed of polysilicon material or metal. The emitter contact is self-aligned to the base contacts by the use of process steps wherein a single mask aperture is used for defining the base contacts and the emitter.
Defensive Publication T104,102 to Ho et al. shows a method of making a bipolar transistor having a polysilicon base contact from which an extrinsic base region is out-diffused. The polysilicon contact is self-aligned with the emitter region.
As advances are made in decreasing the size and increasing the density of bipolar devices, device capacitances and parasitic actions become increasingly limiting factors in device speed. In vertical devices, the electrical base contact-to-substrate capacitance tends to establish parasitic device actions which limit device speed. A lack of symmetry in the base and emitter regions, caused by deficiencies inherent in known fabrication processes, also tends to establish these parasitic actions and hence similarly limit device switching speeds.